• First sighting of U-shaped NAND Cell Architecture!

    Contributed by Jeongdong Choe, Ph. D., Senior Technical Fellow at TechInsights

    We have been waiting for SK hynix 3D NAND products and their cell architecture for many years. We know that SK hynix have been developing several types of 3D NAND cell structure including DC-SF (3-dimensional Dual Control-gate with Surrounding Floating-gate, 2010) and SMArT (Stacked Memory Array Transistor with ONO layer, 2012). However, we have been looking forward to seeing the final cell scheme for their products. TechInsights has just located and performed a quick review of their vertical NAND cell architecture. The SK hynix 3D NAND products, so called 3D version 2, with H28U74301AMR UFS package markings were found in the LG Electronics model F800L, also known as the V20 smartphone. Four NAND dice are in a 64 GB package, which means each 3D NAND die has 128 Gb, likely using MLC (multi-level cell) rather than TLC (triple-level cell). Currently, other major 3D NAND players such as Samsung, Toshiba, SanDisk, Micron and Intel have their 3D NAND products with TLC.

    The die photograph with H27DGS8 die markings consists four planes, which is different from their previous 2D 1x nm planar NAND die as shown in Figure 1.

    Die area is measured with 88.36 mm2, which means the memory density is 1.45 Gb/mm2 on a die with 67.5 % memory array efficiency. The memory density on the die is quite low comparing with other players’ 3D NAND TLC products such as the Micron 32L 3D NAND (2.28 Gb/mm2), Toshiba/SanDisk 48L 3D NAND (2.43 Gb/mm2) and Samsung 48L V-NAND (2.57 Gb/mm2) since the SK hynix H27DGS8 die used for UFS products might be a MLC die instead of TLC die. Referring to memory density on a plane (or a tile for Micron’s 3D NAND die), SK hynix 3D NAND (ver. 2) die has 2.15 Gb/mm2 which is still lower than Micron’s 32L (2.63 Gb/mm2), Toshiba/SanDisk’s 48L (3.45 Gb/mm2) and Samsung’s 48L (3.56 Gb/mm2). Table 1 summarizes a comparison of die information and memory density. Figure 2 and Figure 3 show comparisons of memory density and memory array efficiency from major 3D NAND manufacturers. The memory array efficiency (84.9%) of Micron/Intel’s 3D NAND is higher than others because of their array on CMOS circuits in which the CMOS decoders and sense-amps are sitting under the 3D FG-NAND memory array. The memory efficiency of SK hynix 3D NAND (67.5%) is a little lower than Samsung’s (70.0%) and Toshiba/SanDisk’s (69.9%).

    The SK hynix 3D NAND (version 2) cell structure has a U-shaped vertical NAND string with pipe gates (or back gates) on the bottom portion, which is totally different from the DC-SF vertical NAND structure they showed in 2010. Figure 4 shows the SK hynix 3D NAND array structure. We may be able to name it as a SMArT, however more properly speaking, their new 3D NAND structure is quite different from the SMArT architecture. The SK hynix 3D NAND uses an ONO (oxide-nitride-oxide) based CTF (charge trap flash) and GAA (gate all around) for each cell transistor, but they adopted the U-shaped vertical NAND string. Especially the pipe gates are on the bottom portion to connect two different vertical strings, which is a similar architecture to P-BiCS proposed by Toshiba in 2009. At that time, Toshiba’s P-BiCS Flash was developed to improve their previous BiCS Flash technology such as reliability of memory cells, cut-off characteristics of the lower select gate and high resistance of source line. Toshiba changed the vertical NAND string from a straight shape to U-shape. As with Toshiba, SK hynix uses the U-shaped vertical NAND string likely for a better data retention, wider Vth window, lower resistance of source line and better controlled cut off characteristics of the select gate.

    Another keyword from the SK hynix U-shaped vertical NAND cell array is a floating Si body layer for PGs (pipe gates). An insulating layer separates the silicon body with the pipe-gates or pipe-connections from the substrate. SLs (source lines) and BLs (bit lines) are located on top of the vertical cell array. DSL (drain select line) and SSL (source select line) with three stacked transistors are placed under the SLs and BLs. 43 stacked gates are on the pipe-gates, likely consists of 36 memory cells, DSL/SSL with 3 DSTs (drain select transistors)/SSTs (source select transistors) and 4 dummy wordlines. The ONO-based CTF is used with a macaroni-type Si channel and W control gate. The doped region is under pipe connections. Two different slits are used for process integration, one is on the pipe gates, another is on STI as a block slit. Slit height is measured as 2.39 μm. Three metals are used such as metal 1 (W), metal 2 (Cu) and metal 3 (Al), while Samsung and Toshiba/SanDisk use four metals. Two-step BLPs are used as well. Table 2 summarizes the quick view on SK hynix 3D NAND cell structure.

    According to a quick review of SEM images of SK Hynix 3D NAND cell structure, the process integration for the vertical NAND cell structure likely follows a STI/PG formation followed by a channel hole process including a storage layer and channel hole filling, and then a slit process, gate replacement, SLs and staggered Plugs, and BL formation follow. Two vertical channels are connected through two pipe gates (or pipe transistors) which are used to improve the flow of cell current in the NAND string. The SK hynix 3D NAND version 2 with 36L is the product using the U-shaped vertical NAND string for the first time. SK hynix announced that their 3D NAND version 3 with 48L would be revealed in the market as well in this year. Now, we can say 3D NAND cell architecture is the main stream in the market and industry. All the 3D NAND players have their own and unique cell structure including FG-based and CTF-based cell. Which one would be better for 128 or higher stacked 3D NAND from the process integration and reliability viewpoint? It may be revealed in a couple of years. Please don’t miss out on upcoming TechInsights’ analysis on 3D NAND products.

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