Significant intellectual property has been developed around these algorithms related to error correction, read-retry techniques, wear leveling, garbage collection, data flush, and data trimming, amongst others.
Testing the interface between the controller and the flash memory while controlling the SSD from the host interface can reveal significant details regarding these algorithms as well as what information is stored in what locations (data versus management tables, etc.).
A recent TechInsights investigation uncovered the use of an interesting read retry operation.
Read Retry involves a second read with different parameters (a change in voltage threshold, for example) if the initial page read was inconclusive or had a high error rate.
Samsung has implemented a complex Read Retry for 3D NAND that includes a series of different commands. Investigation also revealed that the controller performs doubling of the number of address cycles from 5 to 10 after certain commands. The extra address cycles seem to include a command structure in addition to modified addresses.
Decreases in cell size and increases in bits per cell decrease the reliability of flash memory – data retention in particular - as the device ages and the number of program/erase cycles increases.
Read Retry improves reliability by varying device parameters to minimize the error rate.
The approach being implemented by Samsung is complex, and provides the ability to adjust a larger number of parameters than competitive approaches, which should provide a more optimal result in terms of data retention and device reliability.
If you, or your client organization, has IP assets related to Memory IC, Consumer SSD, Enterprise Storage, or Controllers, you should be aware of this development in read retry 3D NAND.
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