This report presents a CircuitVision Analysis of the DDR3 delay line and data I/O on the Texas Instruments AM5718AABCXEA Sitara™ ARM application processor. The report contains a full set of schematics and annotated photographs divided into the following sections:
- Architectural Overview
- Delay Line
- I/O Pad
- Symbol Definitions
- Major Findings
- Standard Cells
- Appendix A – Signal List