This report contains the following detailed information:
- Selected teardown photographs, package photographs, package X-rays, die markings, and die photographs
- SEM bevel micrographs through the memory array at the mid-height to show the general layout and at the interconnect level routing the BL to measure the BL pitch
- SEM cross-sectional micrographs across the BL to show the die general view, including the full height of the memory array, as well as high-magnification SEM images at the top of the array to measure the BL pitch
- SEM cross-sectional micrographs across the WL to show the full height of the memory array
- Measurements of vertical and horizontal dimensions of major microstructural features
- Plan-view optical micrograph of the die delayered to the polysilicon layer
- Identification of major functional blocks on the polysilicon layer die photograph
- Table of functional block sizes and percentage die utilization
- High-resolution top metal and polysilicon level die photographs delivered in the CircuitVision software
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