Availability
Published
Product Code
DFR-2306-801
Product Item Code
MTS-SD102AA-500
Device Manufacturer
Moore Threads
Device Type
Graphics Processor
Moore Threads Chunxiao GPU TSMC N7 FinFET HKMG CMOS Process Digital Floorplan Analysis
This report contains the following detailed information:
- Selected teardown photographs, package photographs, package X-rays, die markings, and die photographs
- Scanning electron microscopy (SEM) plan-view micrographs showing the layout of the die at different levels, including fin/shallow trench isolation (STI), gate, contacts, and minimum pitch metals
- Measurements of horizontal dimensions of some of the major layout features, particularly the pitch and track height of standard cells
- Plan-view optical micrograph of the die delayered to the metal gate level
- Identification of major functional blocks on a gate level die photograph
- Table of functional block sizes and percentage die utilization
- High-resolution top metal and gate level die photographs delivered in the CircuitVision software
- Cost of die based on the manufacturing cost analysis of the observed process
The Authoritative Information Platform to the Semiconductor Industry.
