The Advanced CMOS Essentials (ACE) deliverable for logic/SoC chips with planar transistors comprises a concise analyst’s summary document highlighting observed critical dimensions and salient features supported by the following image folders:

Downstream product teardown

Package X-rays, top metal and poly die photographs, non-invasive optical photos of die features

SEM bevel through the logic region and SRAM

SEM cross section of the general device structure, BEOL (metals, dielectrics) and FEOL structures

Two TEM cross sections, orthogonal to the transistor gate fingers showing the lower metals and dielectrics, transistor gates (NMOS and PMOS), isolation, and other FEOL features

The results of TEM-EDS analyses are included in the ACE summary document. The ACE deliverable provides timely competitive benchmarking information and enables cost-effective tracking of technical innovation across a breadth of competitors