The ISP advanced floorplan analysis deliverable includes:

• Selected teardown photographs, package photographs, package X-rays, die markings, and die photographs
• Scanning electron microscopy (SEM) cross-sectional micrographs of the general structure of the die dielectric materials, major features, and transistors
• Measurements of vertical and horizontal dimensions of major microstructural features
• Transmission electron microscopy (TEM) cross-sectional micrographs of the logic transistor, gate dielectric, PMD, ILD 1, metal 1and metal 2
• TEM-based energy dispersive X-ray spectroscopy (TEM-EDS) of logic transistor, gate dielectric, PMD, ILD 1, metal 1 and metal 2
• TEM-based electron energy loss spectroscopy (TEM-EELS) of gate dielectric
• Plan-view optical micrograph of the die delayered to the polysilicon layer
• Identification of major functional blocks on a polysilicon die photograph
• Table of functional block sizes and percentage die utilization
• Memory capacity
• High-resolution CMOS image sensor (CIS) die and ISP polysilicon die photographs delivered in CircuitVision
• Cost of tested die, based on the cost analysis of the observed process

The image set for a standard project is derived from decapsulation of two samples, followed by SEM analysis of a cross-section of the ISP die and optical layout analysis of the ISP die delayered to the gate level.