For a third consecutive year, Arm has updated all three of its licensable client CPUs. The high-end Cortex X4 (Hunter ELP) raises per-clock throughput by 13% on average, implementing 10 instruction decoders—four more than the X3—in a bid to catch up with other CPUs’ single-thread performance. Like last year, Arm focused on improving the power efficiency of its Cortex A cores. To address the Cortex A510’s subpar area efficiency, Arm streamlined the new Cortex A520 (Hayes) by eliminating its third integer ALU. The new Cortex CPUs target client devices such as smartphones, Chromebooks, and PCs. Client devices typically employ heterogeneous clusters of these CPUs, such as a single X4, four A720s, and three A520s (1 + 4 + 3). A PC processor, however, could cluster more cores, such as 10 of the X4 and four of the A720. An updated version of Arm’s DSU cluster controller supports up to 14 CPUs in any combination and 32 MB of L3 cache, twice the capacity of the previous-generation cache. The CPUs’ production RTL is already available, and we expect the first phones using these designs to ship early next year. High-performance embedded processors are another target, but even some recent designs have used the older Cortex A53, A55, and A72 CPUs. If it delivers similar performance as the Cortex A72, the Cortex A520 could motivate customers to upgrade owing to its improved power- and area-efficiency over the poorly received Cortex A510. A future Cortex A520 version with safety and reliability features would provide an upgrade for automotive and industrial customers. The new Cortex CPUs follow last year’s introduction of the Makalu generation, featuring the Cortex X3 and Cortex A715, and a revision to the A510. Although the revised A510 added back 32-bit compatibility, the A520 drops it. The new trio supports the Arm v9.2 instruction-set architecture (ISA), which adds only a few mandatory features to the v9.0 ISA of their predecessor.