Contributed by Jeongdong Choe, Senior Technical Fellow
Posted: June 07, 2017
TechInsights has continued to dig into the process, cell structure and materials analysis of the Intel OptaneTM XPoint memory. We discovered that the Intel OptaneTM XPoint memory die has a 128 Gb/die which is quite a bit lower memory density than the current 3D TLC NAND products as shown in Figure 1. Memory density per die is 2.28 Gb/mm2 for Micron 32L 3D FG CuA TLC NAND, 2.57 Gb/mm2 for Samsung 48L TLC V-NAND, 2.43 Gb/mm2 for Toshiba/WD 48L BiCS TLC NAND, and 1.45 Gb/mm2 SK Hynix 36L P-BiCS MLC NAND. By comparison, the Intel OptaneTM XPoint has 0.62 Gb/mm2.
We know that Micron 32L and 64L 3D NAND products use CuA (CMOS under Array), which means its memory array efficiency is quite high (85%) compared with other 3D NAND products (60~70%). Likewise, memory efficiency for XPoint memory die is more than 90% since the storage elements in the XPoint memory array are located between metal 4 and metal 5. In other words, all the CMOS circuits such as drivers, decoders, BL access, local data and address control are placed under the memory elements which is similar to CuA architecture for 3D NAND. Figure 2 shows a comparison of memory efficiency with current 3D NAND products.
When it comes to memory elements in the XPoint memory array, a double stacked storage/selector structure is used. For the storage element, many candidates such as phase change materials, resistive oxide cells, conductive bridge cells and MRAM cells have been developed. Among them, Intel XPoint memory has adopted chalcogenide-based phase change materials. A GST (Ge-Sb-Te) alloy layer is used for the memory element, which we call a Phase Change Memory (PCM).
For the selector element, many switching devices such as a transistor (BJT or FET), diode and ovonic threshold switch are used. Intel XPoint memory uses another chalcogenide-based alloy with arsenic (As) doped which is different from the memory element material used. This means the selector Intel used on XPoint memory is an ovonic threshold switch (OTS) material. Figure 3 shows cross-section images with double stacked memory/OTS selector elements along the bitline and wordline. OTS selectors are not extended over the middle electrode or bottom electrode. More details can be found in the TechInsights analysis reports.
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