MIPS Releases First RISC-V CPUs

MIPS Inc. has developed its first licensable CPUs implementing the RISC-V instruction set by repurposing older MIPS-compatible cores. The P8700 and I8500 outperform most other RISC-V designs.

Linley Gwennap

Moving beyond its eponymous instruction set, MIPS Inc. has developed its first CPUs implementing the RISC-V architecture. The new products, branded eVocore, are based on older MIPS-compatible CPU designs that have been adapted to the open-source instruction set while also adding new features. The P8700 and I8500 are thus based on proven microarchitectures while delivering greater performance than most other RISC-V CPUs. The two licensable cores are being validated on FPGAs, with RTL general availability expected in 4Q22 for the P8700 and 1H23 for the I8500.

Formerly known as MIPS Technologies, the company has followed a tortuous path through acquisitions by Imagination and Wave Technology before being spun out as an independent company and going through bankruptcy restructuring. Rebranded simply as MIPS Inc., the company emerged from bankruptcy last year owned by Dado Banatao’s Tallwood Ventures.

MIPS decided to direct its efforts to the popular RISC-V architecture, taking advantage of ISA’s broad set of software tools and applications. Although the company must compete against other RISC-V CPU vendors, adopting a common ISA also means that it no longer needs to supply a full range of CPUs. MIPS will instead focus on its I- and P-series RISC-V products rather than continuing to develop M cores for microcontrollers.

The P8700 is a four-issue out-of-order CPU with new multithreading capabilities, targeting applications that need the highest per-core performance. The I8500 is a three-issue in-order CPU that also supports multithreading, delivering strong performance per watt and per unit area. Both CPUs support clusters of up to 64 cores. The company targets eVocore at automotive in-dash and advanced driving applications as well as processors for networking and communications infrastructure.