TSMC Reveals 3nm Process Details

TSMC presented papers at IEDM detailing its 3nm N3 and N3E processes. N3 reduces CPP by 6nm compared with N5. SRAM cells are no smaller in N3E than in N5.

Dick James

To reduce the cost of 3nm manufacturing, TSMC is developing the lower-cost N3E process as an alternative to its original N3. At the recent International Electron Devices Meeting (IEDM), TSMC revealed information about N3E and N3, including details of its FinFlex technique, SRAM size, and metal pitch.

Manufacturing costs have increased because 3nm requires multipatterned extreme ultraviolet (EUV) lithography. TSMC reverted to single-patterning some layers for N3E, but this reduced N3’s density gains. Design-technology-co-optimization (DTCO) techniques, such as FinFlex, recoup some of these losses but not for SRAM. N3E, however, is slightly faster and more power-efficient than N3.

TSMC’s two 3nm processes update the fabrication of contacts and reduce the contacted poly pitch (CPP), resulting in various changes, including to transistor structures, but the improvements are only incremental. FinFETs have reached fundamental limits.

Drive current has been increased by raising fin height, but a ceiling has been reached. Gate lengths cannot shrink further without compromising control of the channel, and fins-per-transistor are reduced to a single fin. Transistor development has hit a wall.

At the same time, DTCO features such as single diffusion breaks, contact-over-active-gate, and FinFlex have yielded their one-time benefits. No node-on-node improvement remains for FinFET processes. Consequently, 3nm will be TSMC’s last before moving to other transistor types.