Last year, Samsung announced the introduction of EUV into their 7LPP process used in the Exynos 9825. Through analysis of the part, we found little difference between their 7LPP process in the 9825 and their 8LPP process in the Exynos 9820.

Now, we are excited to say that we have found Samsung’s true 7LPP process in the Exynos 990, included in their flagship Galaxy S20. This 7nm EUV process delivers, as we expected, Samsung’s highest density layout observed to date.

With a 27nm fin pitch, this disruptive innovation enables a smaller standard cell height of 270nm while maintaining high drive current with a 3/3-fin layout for both NMOS and PMOS transistors.

This shows the increased density achieved with EUV lithography implementation compared to TSMC’s N7 7.5T 3/3-fin layout having a 300nm standard cell height, and 6T 2-fin layout at 240nm standard cell height.

Intel’s 10nm process has a similar 272nm standard cell height, but achieved this with 2/3 fin layout. In addition to pitch scaling, in a surprise implementation, Samsung has introduced a SA-DB (Self Aligned Diffusion Break) that likely reduces performance variation caused by the local layout effect (LLE) of PMOS transistor. This is the first time we found in this device. We also started working on Snapdragon 765G fabbed by same Samsung 7LPP as Exynos 990, it turned out having new features that 243nm standard cell height with 2/2 fin layout and 54nm gate pitch. It should be comparable with TSMC N7 or N7P 2/2 fin layout high density cell.

TechInsights will be examining these part more closely; so far, we have the following analysis planned: