This report presents a Memory Floorplan Analysis of the SK Hynix HFB1A8MQ431A0MR (H25FTMM1 die) 96L 4D NAND. This device features the first PUC structure from SK Hynix, the highest 115 VC gates per NAND string used, and 96 active word lines with 2-deck integration.

This report contains the following detailed information:

• Selected teardown photographs, package photographs, package X-rays, die markings, and die photographs
• SEM cross-sectional micrographs of the general structure of the die dielectric materials, major features, and transistors
• Plan-view SEM micrograph of the die delayered to the WL and BL layers
• Measurements of vertical and horizontal dimensions of major microstructural features
• Plan-view optical micrograph of the die delayered to the polysilicon layer
• Identification of major functional blocks on a polysilicon die photograph
• Table of functional block sizes and percentage die utilization
• High-resolution top metal and polysilicon die photographs delivered in CircuitVision
• Cost of die and tested packaged die, based on the manufacturing cost analysis of the observed process