Memory Process and Integration Challenges: DRAM & NAND

In this Memory webinar, Dr. Jeongdong Choe gave an overview and discussed the latest memory technology trends and challenges, focusing on DRAM and NAND devices.

DRAM cell scaling down to the 10 nm design rule (D/R) has been an ongoing development. Major DRAM players have been developing the next generations, so-called D1b, D1c, and beyond. Which means, DRAM cell D/R might be further scaled down to the single-digit nanometer era. Recently, DRAM cell scaling has slowed due to multiple challenges, including process integration, leakage, and sensing margin. Innovative technologies such as higher-k capacitor dielectric materials, pillar capacitors, recess channel transistors, and HKMG peripheral transistors can be seen in the most advanced DRAM products.

In the NAND space, manufacturers continue to race towards 3D NAND vertical gate numbers to increase storage density. They have planned the next 3D NAND products, including 232L/238L and more up to 4xxL or even 8xxL. To date, five different types of 3D NAND architectures are mainstream such as V-NAND, BiCS, CuA, 4D PUC, and Xtacking.