Comparison: Latest 3D NAND Products from YMTC, Samsung, SK hynix and Micron

As TechInsights continues analysis of YMTC 232-Layer 3D NAND, we thought a comparison was in order. We compared the YMTC’s 1024 Gb (1 Tb) triple level cell (TLC) 232-L 3D NAND with recent 512 Gb TLC 3D NAND dies (see Table 1) we examined from Samsung, SK hynix and Micron.

Up to and including 128-L, 3D NAND had been dominated by Samsung with its single deck process, enabled by its ultra-high aspect ratio (UHAR) hole etch. Samsung still leads the pack with the smallest word line (WL) pitch, which allows more layers to be stacked while minimizing the impact to the process requirements for vertical channel (VC) height and slit depth. While it appears that Samsung may have had the lowest process cost for 128-L, it did not have the lowest die size. This is significant, because the lower the die size area, the more dies that can be fabricated on a 300 mm wafer, and thus more profit.

Samsung started to adopt the cell over periphery (COP) approach at 176-L (Samsung’s 7^th-generation 3D NAND) which lead to a significant die size reduction from its 128-L to 176-L. Similar approaches had been used by Micron from 32-L (Micron’s 1^st-generation 3D NAND) onwards, which Micron termed as CMOS under array, CuA, and by SK hynix from 96-L (SK hynix’s 4^th-generation 3D NAND) onwards, which SK hynix termed as 4D NAND, periphery under cell or PUC). YMTC applied Xtacking at 64-L (YMTC’s 2^nd-generation 3D NAND) to achieve similar benefit of reduced die size, by having the memory array over the periphery circuits. The reduced die size along with increased active word lines (AWLs) drives up the bit density.

The recently acquired YMTC 232-L six-plane 1 Tb TLC die with center X-decoder (see Figure 1) has the highest bit density of 15.03 Gb/mm².

Figure 1: Die image of YMTC 232-L 1 Tb die. TechInsights, 2022.

Chart 1 shows bit density (Gb/mm²) versus number of AWLs. We expect the bit density of the upcoming 232/238L dies to reach approximately 15 Gb/mm². At ISSCC 2022, Samsung 2xx-L test vehicle (with four-plane 1 Tb TLC die with edge X-decoder) has a bit density of 11.55 Gb/mm² [1]. We expect the bit density to increase to above 14.5 Gb/mm² when the production mask set is used. SK hynix 238-L six-plane 1 Tb TLC die with center X-decoder is estimated to be 14.75 Gb/mm² [2] with 34 % increased from previous generation. Micron 232-L six-plane 1 Tb TLC die is stated to be 14.60 Gb/mm² [3].

Chart 1: Bit Density versus Active Word Lines (AWLs). TechInsights, 2022.

Several TechInsights Memory Floorplan and Advanced Memory Essentials reports informed this comparison article. Subscribers to our NAND & DRAM channels can access the reports below in our Platform. If you are not a subscriber, but are interested in our reports, please contact us.

At 232/238-L, YMTC showed the highest bit density and Samsung is projected to have the lowest bit density. What does this mean for the NAND market? Does this mean that Samsung will be dropping out of the race? Certainly not. One of the more important factors to consider is the overall cost, and thus the metric of cost/bit is the most ideal data for comparison. TechInsights, through our recent acquisition of IC Knowledge, is working toward calculating cost/bit, and should have this information available in 2023. IC Knowledge is the world leader in cost modeling of semiconductors. Click here if you would like to learn more about this acquisition.