Movellus Offers Core-level Dynamic Voltage Scaling

Movellus’s licensable Aeonic Power on-die voltage regulator (ODVR) technology enables dynamic voltage scaling circuity to be integrated in silicon at a core level, enabling fine-grained power control and the creation of virtual power islands around individual cores on the same chip. Aeonic Power also simplifies a chip’s power delivery network by reducing rails, offering localized static potential drop (iR) compensation, noise suppression, and providing advanced telemetry.

With the increased compute capability required to meet demands for AI and other computationally intensive applications comes a corresponding increase in power demand that has become a prominent concern and gating factor for chip designers. Some studies show that as much as 40% or more of datacenter operating costs are in power and cooling, including equipment, and the rise of generative AI workloads will only exacerbate the problem. Chip firms are achieving significant power savings using chip-level dynamic voltage scaling (DVS) techniques, and the leading chip vendors such as Intel and AMD are using it down to the core level. Movellus’s Aeonic Power intellectual property (IP) makes core-level DVS technology available to chip designers at companies of all sizes.