Posted: June 21, 2017
Contributing Authors: Ray Fontaine
At the time of the IISW paper submission deadline in April, we hadn’t yet received the Sony Xperia XZs with 3-layer stacked Motion Eye camera. The technology development had been announced at ISSCC 2017, and we did get results in time for the presentation material (see also the blog by Dick James). Work on the IMX400 project continues and we look forward to publishing our report in a few weeks. Enjoy Part 2, where we discuss the trends in wafer-to-wafer interconnect and other features of stacked chips.
Stacked Chip Image Sensors
The development of low-temperature wafer bonding and various wafer-to-wafer interconnect techniques have been key enablers for stacked image sensors. Two-die stacks, comprising a back-illuminated CIS and mixed-signal image signal processor (ISP), have emerged as the dominant configuration for leading smartphone camera chips. The CIS portion can be considered a 'dumb' chip carrying only an active pixel array. Most of the signal chain and digital processing is partitioned onto the ISP and systems application processor.
| Chip Vendor | Year | Stacked CIS Foundry/Gen. | Stacked ISP Foundry/Gen. | |||
|---|---|---|---|---|---|---|
| Sony | 2013 | Sony 90 nm | Sony 65 nm | |||
| Sony | 2014 | Sony 90 nm | TSMC 40 nm | |||
| Sony | 2016 | Sony 90 nm | TSMC 28 nm | |||
| OmniVision | 2015 | XMC 65 nm | XMC 65 nm | |||
| OmniVision | 2016 | TSMC 65 nm | TSMC 65 nm | |||
| Samsung | 2015 | Samsung 65 nm | Samsung 65 nm | |||
| Samsung | 2016 | Samsung 65 nm | Samsung 28 nm HKMG | |||
| Sony | ISSCC 2017 |
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Table 2. Noteworthy Stacked Chip CIS/ISP Configurations
A. Stacked Chip Fabrication Technology Trend
The recent manufacturing trend for back-illuminated CIS chips in a stacked configuration seems to have stabilized at the 90/65 nm process generation. There doesn’t appear to be a driver for further scaling of the CIS chip technology generation, although recently sub-65 nm processing has been observed in 1.0 µm generation pixel structures to facilitate narrower W aperture grid metal. Samsung’s 28 nm high-k metal gate process is currently in use for stacked ISPs [14] and the ISP scaling trend is expected to continue towards the latest advanced CMOS technology generations.
Fig. 1. Sony 1st gen. dual TSVs (a), 2nd gen. unified TSV (b), 1st gen. DBI (c)
Fig. 2. OmniVision 1st gen. butted TSV (a), 2nd gen. unified TSV (b), Samsung butted TSV (c)
B. Wafer-to-Wafer Interconnect
Sony was first to bring stacked CIS chips to market, initially by implementing homogenous wafer-to-wafer bonding (oxide bonding) and through-silicon-vias (TSVs) in 2013 and later with Cu-to-Cu hybrid bonding, also known as Cu2Cu bonding or DBI, in 2016 [18,19]. The first generation TSVs, deployed as three major arrays above and along both sides of the active pixel array, featured a dual TSV structure for the row/column interconnect of a 1.12 µm generation pixel array. One shallow, Cu-filled TSV contacted the back of a metal 1 CIS metal pad, one deep, Cu-filled TSV contacted a top metal Al ISP pad, and final interconnect was achieved with a planar Cu metal strap. The dual TSV structures had a rectangular footprint and were placed on a 6.0 µm x 9.0 µm orthogonal pitch [20].
TSony simplified its TSV process flow in 2015 by introducing a single, or ‘unified’, structure which contacted both CIS and ISP landing pads with one cylindrical vertical interconnect [21]. These structures were placed on a 9.1 µm minimum orthogonal pitch, although TSV rows were half-pitch staggered from neighboring rows.
OmniVision’s first observed stacked chips, fabricated on the PureCel-S platform with foundry partner XMC, featured a ‘butted’ TSV structure in which a single, wide TSV contacted both a CIS and ISP pad structure. The rectangular structures, in use on a 1.12 µm pixel generation chip, had a 5.2 µm x 9.9 µm orthogonal pitch [22]. OmniVision later adopted a unified TSV structure for its 1.0 µm pixel generation PureCelPlus-S chips, fabricated by foundry partner TSMC. These structures were placed on a 4.0 µm x 4.1 µm orthogonal pitch [10].
The observed Samsung stacked chips in production also feature a butted TSV structure, but instead use a W-based TSV window liner for vertical interconnect. The first-generation Samsung TSVs, incorporated on a 1.12 µm pixel generation chip, were placed on an 8.8 µm x 9.6 µm orthogonal pitch [23].
Sony recently shifted its interconnect strategy to incorporate DBI initially as a TSV array replacement. This implementation of DBI featured active DBI pads in the same regions as had been occupied by TSVs, with dummy DBI pads covering most of the active pixel array and peripheral regions. The current state of the art for production DBI is square pads having a 3.0 µm width placed on a 6.0 µm orthogonal pitch. A DBI pitch of 1.6 µm has been reported [24] and it is expected that future generations of DBI-enabled chips will feature per-pixel interconnect.
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References
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[13] Samsung press release, Mar. 2016.
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[17] Oppo R9s landing page, Oct. 2016.
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[19] Invensas corporate web site, Apr. 2017.
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