Intel has defined the most significant update to the x86 instruction set since its extension to 64 bits. The Advanced Performance Extensions (APX) double the number of general-purpose registers to 32 and allow integer instructions to specify a unique destination register. In parallel, the company has defined Advanced Vector Extensions 10 (AVX10) to clean up AVX 512. Intel reports that APX’s register-related changes reduce the number of loads and stores in compiled code by 10% and 20% respectively, which should speed up program execution and lower CPU energy consumption. APX also adds to the x86 ISA’s predicated-execution capabilities, which should help compilers eliminate performance-sapping, hard-to-predict branches. Whereas APX defines new ISA capabilities, AVX10 addresses problems with AVX 512 that have made it awkward for programmers to use and have rendered it unavailable in recent generations of Intel’s PC processors. AVX10 clears the path for the newest vector operations to run on the company’s small, efficient CPUs (E cores). The first processor to implement basic AVX10 features will be Granite Rapids, a server processor due in 2024. The second-generation AVX10.2 will coincide with APX, and we expect Intel to also roll out the streamlined x86 S architecture at the same time. Because these are substantial ISA changes, they are likely to be made in an all-new CPU Intel is developing for the Lunar Lake processor due to be in PCs available in 2025. The new x86 extensions are part of Intel’s effort to regain clear efficiency and performance advantages over AMD. Related projects include the redesigned CPU and several process nodes. APX is the most significant of the extensions, increasing throughput on the integer code that makes up the bulk of software. Adding capabilities found in forty-year-old RISC architectures, it’s long overdue.