Power Semiconductor Subscriptions

Provides in-depth process analysis for GaN, SiC, and Si power devices, providing comprehensive coverage of device metrics and salient features. Analysis includes detailed structural and material analysis using techniques such as SEM, TEM, and SCM/sMIM, covering package and die images/X-rays, SEM planview and cross-sectional images with annotated SEM-EDS material analysis conclusions, and cross-sectional TEM images with annotated TEM-EDS/EELS analysis conclusions for GaN devices, and cross-sectional and planar SCM (sMIM) analysis for Si and SiC.

Analysis Coverage

• Device metrics and salient features
• Package x-rays and die photos
• SEM plan-view images and cross-sectional SEM images
• Cross-sectional TEM images and material analysis
• Analyst briefing

Provides in-depth process flow analysis detailing the manufacturing steps to fabricate innovative SiC and GaN power devices from wafer-in to wafer-out. Analysis includes process architecture, mask list, and integration-level process steps, layout (.GDS) decomposed into process layers, and emulated device structure, tool type as well as design rules, layer dimensions, and process assumptions.

Process Flow Analysis (PFA)

• Reports showing process architecture, mask list, and integration-level process steps

Process Flow Full Emulation (PFF)

• Expands upon the detail provided in PFA reports
• Layout GDS fully decomposed into process layers
• Provided PDF reports are built using Synopsys Process Explorer
• Manipulate report data in Synopsys (requires Synopsys license)
• Process Flow Full Emulation reports with supporting images
• Design technology interaction analysis
• Detailed explanation of process integration from wafer-in through wafer-out
• Process steps, materials, equipment type, unit process
• SEM and TEM cross-sectional and top-view images \ Layer annotations, specific process module, assumptions

Provides in-depth process (structural and materials) analysis of power-management devices based on bipolar-CMOS-DMOS (BCD) technology, integrated voltage regulators (IVR), and other innovative power management devices. Analysis of PMICs found in devices in the mobile, automotive, and other industries, covers structures and materials using SEM, TEM, sMIM/SCM, SEM-EDS, and TEM-EDS/EELS as required. Also included are package and die images and salient features with a comparison summary.

The fundamentals of the Power subscription, Power Management IC (PMIC) Process Analysis provides:

• ID Images
  • Package photos and X-rays
  • Includes optical images at die level and gate level of PMIC (from backside poly images)
• Annotated die photo with sample locations (SEM, TEM etc)
  • Annotated images of gate level sample, detailing major circuit blocks e.g. logic, memory, power device etc
• SEM – Power transistor analysis
  • Plan view across bevel of the power transistor
  • Cross sections of the power transistor die (across the gates)
• SEM – control circuitry
  • Cross section of the controller region
• SEM-EDS – materials analysis results only, not the spectra
  • All present metal and dielectrics
• sMIM/SCM – Power transistor
  • Plan view across bevel of the power transistor
  • Cross sections of the power transistor region (across the gates)
• TEM
  • Cross-sections of power device gate oxide
  • Cross-section + TEM EDS of connecting regions such as vias, interfaces between metal layers and dielectric.
  • Cross-section of isolation region interfaces e.g. SOI, trench or deep doping wells
• Salient features and comparison summary slide
  • Dielectric layers composition & thickness
  • Metal layers composition & thickness
  • Critical feature horizontal & vertical dimensions