This report contains the following detailed information:
- Selected teardown photographs, package photographs, package X-rays, die markings, and die photographs
- Scanning electron microscopy (SEM) cross-sectional micrographs of the general structure of the die dielectric materials, major features, and transistors
- Measurements of vertical and horizontal dimensions of major microstructural features
- Plan-view optical micrograph of the die delayered to the polysilicon level
- Identification of major functional blocks on gate level die photograph
- Table of functional block sizes and percentage die utilization
- High-resolution top metal and polysilicon die photographs delivered in the CircuitVision software
- Cost of die and tested packaged die, based on the manufacturing cost analysis of the observed process
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