The Impact of Standard Cell Width on Future Innovation

Module two dives into logic scaling by focusing on standard cell width, setting the foundation with a recap of module one. The earlier discussion highlighted Moore's Law as both a technical and economic observation, along with Dennard scaling, which provided a "golden age" of device improvement by simply shrinking gate length. However, scaling limitations arose, leading to innovations like FinFETs, and the journey from there to today's horizontal nanosheets and beyond is detailed in this series.

Logic scaling is the initial focus because system-on-chip designs dedicate roughly half of their die area to logic. The first few modules, including this one, concentrate on shrinking the standard cell, specifically its width and later height, to improve logic design efficiency.

The key to standard cell scaling lies in the contacted poly pitch, a critical factor determining cell width. It involves components like gate length, spacer thickness, and contact width, all of which face scaling limitations due to physical constraints. This module explores these elements in-depth, explaining how manufacturers like Intel, Samsung, and TSMC have historically scaled contacted poly pitches and how future scaling can be achieved. Techniques such as spacer thinning, contact resistance reduction, and multi-gate structures like FinFETs and gate-all-around devices are discussed as part of the solution.

Subsequent modules will address the height of standard cells and performance considerations before moving on to SRAM, analog IO, and concluding with future roadmaps.