Performance and Efficient Cores in Advanced Processors
Learn how multi-threaded execution and heterogeneous core designs, like Arm's "big.LITTLE," are revolutionizing processor architecture for high performance and power efficiency in advanced mobile devices.
High-performance on-die cache memory access time is outpacing the slower system memory access times causing the processor core to be stalled waiting for a system memory read with the required data. Introduction of “multi-threaded” instruction pipeline execution is now a common architecture strategy in most advanced processors. This report discusses the significant changes in processor architecture design that address the more diverse program workloads needed in today’s advanced mobile devices. Specifically, a heterogeneous core design approach was adopted (the most prevalent example is the availability of disparate cores from Arm, known as the “big.LITTLE” approach). This architecture provides a solution to the wide variety of computational throughput demands to deliver low-cost withy power efficiency.
