Intel 10 nm Logic Process Analysis (Cannon Lake)

Posted: June 12, 2018

Intel 10nm Logic Process Analysis

Intel 10nm Logic Process Analysis

TechInsights has found the long-awaited Cannon Lake - the Intel 10 nm logic process inside the i3-8121U CPU, used in the Lenovo IdeaPad330.

This innovation boasts the following:

  • Logic transistor density of 100.8 mega transistors per mm2, increasing 10nm density 2.7X over the 14nm node
  • Utilizes third generation FinFET technology
  • Minimum gate pitch of Intel’s 10 nm process shrinks from 70 nm to 54 nm
  • Minimum metal pitch shrinks from 52 nm to 36 nm

Process Highlights:

  • Deepest scaled pitches of current 10 nm and upcoming 7 nm technologies
  • First Co metallization and Ru usage in BEOL
  • New self-aligned patterning schemes at contact and BEOL

Design Highlights:

  • Hyperscaling via 6.2-Track high density library
  • Contact on active gate (COAG) cell-level usage

Intel 10nm Logic Process Analysis